1. Field of the Invention
The present invention relates to a method of manufacturing semiconductor device, particularly to a method of forming a gate electrode for a MOSFET, and more particularly to a method of forming a gate electrode with a titanium polycide in which a titanium silicide layer is formed on a polysilicon layer.
2. Description of the Related Art
In general, a gate electrode of a MOS transistor has been formed of a doped polysilicon layer. However, as high integration of semiconductor device, the line widths of a gate electrode and other patterns become fine. Recently, the line width is reduced below 0.15 .mu.m. Therefore, there are problems that it is difficult to apply the doped polysilicon layer to a gate electrode material in a high speed device, since the doped polysilicon layer has a high resistivity. These problems are also growing more and more serious as the high integration of the semiconductor. To overcome these problems, a gate electrode with a titanium polycide structure in which a titanium silicide layer is formed on the polysilicon layer, is applied to a semiconductor device over 1 GDRAM.
Here, the titanium silicide layer is formed by two methods as follows.
A first method deposits a titanium(Ti) layer on a polysilicon layer and performs annealing, to react the Ti with Si of the polysilicon layer, thereby forming a titanium silicide (TiSi.sub.2) layer. A second method deposits a TiSix layer of an amorphous phase on a polysilicon layer by physical vapor deposition(PVD) using a sputtering target of TiSix(x=1.8.about.2.5) and performs annealing, thereby forming a TiSi.sub.2 layer of a crystalline phase.
FIG. 1A to FIG. 1E are cross sectional views showing a process of forming a gate electrode with a titanium polycide according to a prior art, using the second method.
As shown in FIG. 1A, a gate oxide layer 11 is formed on a semiconductor substrate 10 and a doped polysilicon layer 12 is deposited thereon.
As shown in FIG. 1B, a TiSix layer 13 of an amorphous phase is deposited on the polysilicon layer 12 by physical vapor deposition(PVD) using TiSix target. Sequentially, rapid thermal process(RTP) is performed at a selected temperature for several seconds, to transform the TiSix layer 13 of the amorphous phase into a TiSi.sub.2 layer 13a of a crystalline phase, as shown in FIG. 1C. A mask nitride(or oxide) layer 14 is then deposited on the TiSi.sub.2 layer 13a, for a self-aligned contact(SAC) process which will be performed after.
As shown in FIG. 6D, the mask nitride layer 14, the TiSi2 layer 13a, the polysilicon layer 12 and the gate oxide layer 11 are patterned by etching process, to form a gate electrode.
Thereafter, for removing damage due to the etching process and polysilicon residues and improving the reliability of the gate insulating layer by forming bird's beak thereon, a gate re-oxidation process is performed by a well-known method, to form an oxide layer 15 on the side wall of the gate electrode and on the surface of the substrate 10.
However, when performing the gate re-oxidation process, the side wall of the TiSi.sub.2 layer 13a is excessively oxidized, to occur in abnormal oxidation of the TiSi.sub.2 layer 13a, as shown in FIG. 1E, thereby increasing resistivity of the gate electrode. The abnormal oxidation of the TiSi.sub.2 layer 13a is influenced by mole ration x of Si to Ti(Si/Ti) in the TiSix sputtering target for depositing TiSix layer. For example, in the case of lowering the mole ratio x of Si/Ti below about 2.1, the abnormal oxidation is extremely occurred, in case raising the mole ratio x of Si/Ti above about 2.4, the abnormal oxidation is almost never occurred. Namely, in case that Si content of TiSix sputtering target is excessive, stoichiometrically, the oxidation ratio of the TiSi.sub.2 layer 13a is equal to that of the polysilicon layer 12.
While it is of benefit to the gate re-oxidation process to raise the mole ratio x of Si/Ti in TiSix sputtering target, there is problem that particle increases with increasing x. Therefore, it is limited to utilize TiSix sputtering target having Si content above 2.4.
In general, TiSix sputtering target has mole ratio x of Si/Ti of 1.8 to 2.5. In FIG. 2, a dot line A shows that in case raising mole ratio x of Si/Ti in TiSix sputtering target, Si is excessive, thereby forming increasing particles. Furthermore, a dot line B shows that in the case of lowering the mole ration x of Si/Ti in SiTix sputtering target, Si is deplete to create pore in the target, thereby creating particles. A solid line C shows total particle distribution which occurs considering both cases described above. As a result, when utilizing TiSix sputtering target of the mole ratio x of Si/Ti of about 2.05 to 2.10, particle creation is minimized.
Accordingly, it is impossible to overcome problems such as particle creation and abnormal oxidation when forming gate electrode, using a prior art as above described.